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posted by  H-A on 11/5/2009 2:00:07 AM  |  status: Closed  |  Earned Karma: 25

assembly2

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What is meant by instruction pipelining in RISC processor? What are

'/ the problems that may accompany this technology?

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posted by shirlee on 11/5/2009 3:03:13 AM  |  status: Live
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An instruction pipeline is a technique used to increase the instruction throughput i.e., the number of instructions that can be executed in a unit of time. The process of instruction execution is done in stages and each of these will be pipelined.

In a typical lifecycle of an instruction it is first fetched from the part of memory the code is stored, then decoded to determine which registers keep the needed operands in memory and then executed.

This technology may not work well when there exists data dependency. A data dependency occurs when an instruction depends on the results of a previous instruction. It affects long pipelines more than shorter ones since it takes a longer period of time for an instruction to reach the final register of a long pipeline. Also it is not possible to reduce the execution time of the fragments if they are dependent

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