Embedded Systems II – Homework

 [Question 1]

Describe, in general terms, the operation of the following types of I/O interfaces.

• Software-polled

• Interrupt-driven

• DMA-driven- Direct Memory address controller.

Which are best suited for which classes of applications?

 Which interfaces have the highest level of required hardware support?

[Question 2] POLLED I/O: Determine the software polling overhead In terms of the fraction of CPU time consumed - for the following three types of device. Assume that the number of clock cycles for a polling operation is 100; that the processor executes with a 100MHz clock; and that no data transfer can be missed.

• A pointing device such as a mouse that must be polled 25 times a second to ensure that we do

not miss any movement.

• A CD-ROM drive that transfers data to the processor in 512 byte units at a time and that has a

data transfer rate of 250KB/second.

• A hard disk that transfers data in 4KB units and that can transfer at 5MB/second.

[Question 3] POLLED I/O vs. INTERRUPT I/O

Discuss the advantage(s) that interrupt-driven I/O has over polled I/O. Illustrate your answer by calculating the fraction of CPU time consumed for the devices given above assuming that the overhead for each transfer, including the interrupt, is 100 clock cycles and that each device is only actively transferring 25% of the time. Why is the percentage of time that a device is active of importance in  comparing polled I/O to interrupt-driven I/O?

[Question 4] NIOS II Interrupts

An interrupt service routine consists of two nested loops --- a small inner loop and a much larger outer loop. Here is the general structure of the program:

The memory addresses are in decimal. With the exception of the two branches at addresses 239 and 1200, all instructions utilize straight line sequencing. Each address contains one instruction. The program is to be run on each NIOS system (II/e, II/s, and II/f). Assume that each instruction takes 1 cycle to execute on each processor, calculate how many interrupts can be handled in 1 second of time, assuming each processor runs at 50MHz. Hint: First calculate how many instructions are executed.

[Question 5] Interrupts I/O

Consider a system with a microprocessor that scans the status of an output I/O device every 20 milliseconds. This is accomplished by means of an interrupt timer alerting the processor every 20 milliseconds. The interface device includes two ports: one for status and one for data output. How long does it take to scan and service the device given a clocking rate of 8MHz. Assume for simplicity that all instructions take 1 clock cycle and that the scanning and servicing take 100

instructions and there is 200 cycle overhead for entering an interrupt routine, and 40 cycle overhead for leaving a routine.

[Question 6] DMA I/O

Consider the scenario where the hard disk is under DMA control and the transfer granularity to/from the disk is 16KB and it is actively transferring 100% of the time. What fraction of the CPU time is consumed if the initial set-up of a DMA transfer takes 1000 processor clock cycles and the handling of the interrupt at DMA completion requires 500 processor clock cycles? Ignore any impact from bus contention between the processor and DMA controller. Assume that the

bus capacity for transfer using the DMA is 4MB/s.

[Question 7] I/O Performance.

Compare and graph the overhead involved in Interrupt vs. Polled I/O with realistic values. The I/O device being examined is a Hard-Drive which has a maximum throughput rate of 36.29 MB/s. The microprocessor being examined is assumed to have a 50MHz clock frequency. Assume that the three I/O synchronization mechanisms being compared are:

• Polled I/O - Has a transfer granularity of 128 bytes / transfer. The polling routine takes 800 cycles when there is data present, and 250 cycles when no data is present.

• Interrupt I/O - Has a transfer granularity of 256 bytes / transfer. The interrupt handling routine requires 1650 cycles to execute.

• DMA I/O - Has a transfer granularity of 128Kbytes. The initialization of a DMA transfer requires 1200 cycles, the finalization of a DMA transfer requires 600 cycles. You may ignore bus contention in your calculations.

Now, consider the overhead of each of these systems, if the fraction of the throughput of the device which is being utilized is 100%, 80%, 50%, 25%, 5%. Your data should be presented in a table, where the rows are the percentages, and the columns are the I/O mechanisms. This is convenient to do in Excel or an equivalent spreadsheet. Graph your table, submit the graph with your solutions. When discussing all three I/O mechanisms - is it possible to find a

synchronization mechanism which is the consistent (in all cases) best performer? Is it possible to find a consistent worst performer?