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posted by  needhelp11 on 11/4/2009 4:05:22 AM  |  status: Closed  |  Earned Karma: 50

Latches&Flip Flops

Course Textbook Chapter Problem Needs by
Digital Circuits Digital Design (3rd) by Mano 5 N/A 11/6/2009 at 5:00:00 PM
Question Details:
1 Latches
1. Draw the gate level diagram for an SR latch.
2. Draw the waveforms for S, R, Q, and Q’ for a SR Latch. Assume that Q is initially unknown,
put X’s for Q and Q’ until those outputs are initialized by S or R. Assume that the NOR gates
inside the latch have a 1 ns gate propogation delay. The S and R inputs are shown in figure
1.


Figure 1: Inputs for the SR latch in problem 1
2 Flip Flops
3. Draw a Master-Slave flip flop that triggers on a falling clock edge using only D latches and
inverters.
4. Draw a Master-Slave flip flop that triggers on a rising clock edge using only D latches and
inverters.
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posted by mbd (MNK) on 11/4/2009 7:59:25 AM  |  status: Live
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SR Latch............
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